Homework on Speed Limits in Chips, 2002 version (solutions)

Feel free to work on the homework in groups. The work you hand in, however, should reflect your understanding of the material and be in your own words. Students who turn in identical (or close to identical) homework assignments will be asked to explain their answers orally to the TA or prof. A student who cannot explain how he or she arrived at a given answer will be charged with academic dishonesty.

You should justify all of your answers for full credit.

Increasing Interconnect Speed (from Dr. Lu's Lecture)

1.	What is the major issue that would make computer chips run slower in the future even though the tranistors on the chip are getting smaller and higher density? Capacitance. Time delays are proportional to resistance and capacitance. Resistance drops with smaller distance, but capacitance increases - at best, the time delays remain constant.
2.	Explain why three-dimensional (3D) chip architecture is not commonly used now.