As the density of devices in a given area of a semiconductor continues to increase, interconnect processing in a plane has become difficult and limits the performance of the device. Thus, the current model is to build interconnects in a three dimensional network of vertical and horizontal wiring. To build three dimensional networks of wires, we must planarize the wafer at each horizontal level to make further processing simpler and accurate. Professor Shyam Murarka and a team of researchers at the Center have found a method to combine both mechanical smoothing, similar to gentle sandpaper, and chemical smoothing to planarize the semiconductor wafer. This process is called Chemical Mechanical Polishing, and it allows more layers of interconnections to be deposited on the silicon wafer, enabling much higher device integration onto a single chip.