Focus Center, New York: Rensselaer - Task Ic

Major Task:
Electrical Interconnects

Sub-task:
Hyper-Integration Technologies: Processing and Design

Primary Investigator:
Jian-Qiang "James" Lü

Goal: Establish technology platforms of, design circuits and architectures enabled by, and perform modeling and simulations on wafer-level three-dimensional (3D) hyper-integration for future chips with high performance, high interconnectivity, high functionality, and simplified processing with low cost, and for heterogeneous system integrations with mixed signal, wireless, THz, optical devices as well as nano devices and bio-chips/MEMS.

3D Hyper-Integration at Wafer-Level

Wafer-level three-dimensional (3D) hyper-integration is one of the emerging chip architectures/technologies for future chips with high performance, high interconnectivity, high functionality, and simplified processing with low cost, and for heterogeneous system integrations. The Rensselaer 3D hyper-integration platform starts with fabrication of functional components (e.g., logic and memory) on separate wafers, followed by wafer aligning, bonding, thinning and vertical inter-wafer interconnection to integrate these functional components in a 3D stack. 3D integration offers significantly increased interconnect performance relative to 2D chips by reducing global interconnect delays, and is a promising approach to significantly increase functionality by heterogeneous integration of materials, devices, and signals. 3D integration has been aggressively pursued recently in the research community, with initial focus on microprocessors, application specific ICs (ASICs), and memories; and is extended to integration of RF, analog, optical, and micro-electro-mechanical systems (MEMS) onto silicon platforms.

TASK Ic PG 2

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