Tong Zhang
— Assistant Professor of Electrical, Computer & Systems Engineering
Rensselaer Polytechnic Institute

Education
— Ph.D., Electrical and Computer Engineering, Uinversity of Minnesota, 2002
M.S., Electrical Engineering, Xi'an Jiaotong University, China, 1998
B.E., Electrical Engineering, Xi'an Jiaotong University, China, 1995

Career Highlights:

Research Areas:
The general research theme of Zhang's group is VLSI architecture design and implementation for signal processing and communication systems.  Current research activities include advanced channel coding system VLSI design for hard disk read channel; multi-input multi-output (MIMO) signal processing VLSI architectures for wireless local area network; on-chip error-correction system design and implementation for multi-level Flash memory; error-tolerant design for very deep sub-micron integrated system; self-timed VLSI design for adaptive signal processing system.

Select Publications
F. Sun and T. Zhang, "Parallel High-Throughput Limited Search Trellis Decoder VLSI Design", IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 13, no. 9, pp. 1013-1022, Sept., 2005

S. Chen and T. Zhang, "Self-Timed Dynamically Pipelined Adaptive Signal Processing System: A Case Study of DLMS Equalizer for Read Channel", IEEE Transactions on Circuits and Systems I ,Vol. 52, no. 7, pp. 1338-1347, July, 2005

H. Zhong and T. Zhang, "Block-LDPC: A practical LDPC coding system design approach", IEEE Transactions on Circuits and Systems I,vol. 52, no. 4, pp. 766-775, April, 2005

T. Zhang and K. K. Parhi, "Joint (3,k)-Regular LDPC Code and Decoder/Encoder Design", IEEE Transactions on Signal Processing vol. 52, no. 4, pp. 1065-1079, April, 2004

T. Zhang, "A High Throughput Limited Search trellis Decoder for Convolutional Code Decoding", IEEE International Symposium on Circuits and Systems (ISCAS), May 2004

S. Chen and T. Zhang, "Run-time Reconfigurable Adapative Signal Processing System with Asynchronous Dynamic Pipelining: A Case Study of DLMS ADFE", to appear IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation, Oct. 2004

T. Zhang and K. K. Parhi, "An FPGA Implementation of (3,6)-Regular Low-Density Parity-Check Code Decoder", EURASIP Journal on Applied Signal Processing, special issue on Rapid Prototyping of DSP Systems vol. 2003, no. 6, pp. 530-542, May 2003

T. Zhang and K. K. Parhi, "Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials", IEEE Transactions on Computers, vol. 50, pp. 734-749, July 2001

Contact Information:
Tong Zhang
Assistant Professor
Electrical, Computer and Systems Engineering Department
Rensselaer Polytechnic Institute (RPI)
110 Eighth Street
Troy, N.Y. 12180 USA
Ph: (518) 276-2945
Fax: (518)276-8761

E-mail: tzhang@ecse.rpi.edu

http://www.ecse.rpi.edu/homepages/tzhang

 

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