Professor of Electrical, Computing,
and Systems Engineering,
Rensselaer Polytechnic Institute
Ph.D., Electrical Engineering, University
of Illinois, 1961
M.S., Electrical Engineering, University of Illinois, 1957
B.S., Engineering Physics, University of Illinois, 1955
Rose began his professional career in 1961 as a physicist at the General Electric Corporate Research Laboratory. He joined Rensselaer’s Electrical Engineering Department as an associate professor in 1965, and was promoted to professor in 1971. He received Rensselaer’s Distinguished Faculty Award in 1970, and is a member of the American Association for the Advancement of Science (AAAS) as well as a Senior Member of the Institute of Electrical and Electronics Engineers (IEEE).
He currently serves on the program committee of the IEEE/Semiconductor Equipment and Materials International (SEMI) Advanced Semiconductor Manufacturing Conference. He and his students have been Phase II participants in the SRC-sponsored Cu Design Challenge and the SRC SiGe Design Challenge.
Rose also served as co-editor with A. Reisman of a Special Issue of the Proceedings of the IEEE on Thick and Thin Films for Electronic Applications in October 1971 and was an organizer of the Materials Research Society’s Conference on Interface Control of Electrical, Chemical, and Mechanical Properties with S.P. Murarka, T. Ohmi, and T. Seidel in November 1993.
For the past several years, Rose’s research has been focused on design approaches for microelectronics. This led to the development of the Rensselaer Interconnect Performance Estimator (RIPE), a. software tool for early estimation of microprocessor chip performance and power, when performance is constrained by interconnects. RIPE’s models are described in Modeling Microprocessor Performance, a book Rose co-wrote with Bibiche Gueskens. More recently, he has been involved in the development of PRACTICS (PRedictor of Access and Cycle Time for Cache Stack), which models memory performance and power. This has been used to demonstrate the advantages of 3D integration.
Recently, Rose has been involved with his students in the design of Analog-Digital Converters using SiGe BiCMOS technology and error correction in flash memory chips. Earlier, he and his students at Rensselaer have researched the use of superconducting films as high-performance interconnects and radiation detectors, the growth and properties of semiconductor materials (especially nitrides and silicon-rich oxides), laser processing, neural networks, and VLSI testing.
As a director of the Rensselaer Research Site for the National Science Foundation’s Industry/University Cooperative Research Center for Microcontamination Control (CMC), he was involved in defect analysis for improved BEOL yield. He also has had a long involvement with cryoelectronics -achieving improved processor performance by low temperature operation. Since interconnects increasingly dominate processor performance, low temperature operation with normal metal offers greater reduction in resistance than changing materials from aluminum to copper. Through his collaboration with Intermagnetics General Corporation, high temperature superconducting interconnects were fabricated and characterized for high off-chip performance.
Rose co-developed and taught a short course on very large-scale integrated (VLSI) Yield Enhancement from 1990 through 1994, with H.G. Parks, a professor at the University of Arizona. Rose also has developed and taught courses on the physical basis of solid-state electronics, electronic properties of materials, yield management and statistical process control, and VLSI design.
F. Sun, S. Devarajan, K. Rose, and T. Zhang, "Multilevel Flash Memory On-Chip Error Correction Based on Trellis Coded Modulation", IEEE International Symposium on Circuits and Systems Kos, Greece, (May 2006).
A. Zeng, J. Lu, K. Rose, and R.J. Gutmann,
"First-Order Performance Predicition of Cache Memory with Wafer-Level Integration", IEEE Design & Test of Computers 548-555,(November-December 2005).
A. Zeng, J.-Q. Lu, R.J. Gutmann, and K. Rose, "Wafer-level 3D Manufacturing Issues for Streaming Video Processors", IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Boston, 247-251, (2004)
S. Devarajan, R.J. Gutmann, and K. Rose, "A 87dB, 50 MS/s SiGe BiCMOS Sample-And-Hold Residue Amplifier", IEEE International Symposium on Circuits and Systems, (May 2004).
M. Gupta, G. Rajagopalan, C.K. Hong, J-Q. Lu, K. Rose, and R.J. Gutmann, "Planarization Yield Limiters for Wafer-Scale 3-D IC's", IEEE/SEMI Advanced Semiconductor Manufacturing Conference, Boston, (2002).
K. Rose, B. Geuskens, R. Mangaser, and C. Mark, "A Comprehensive Look at System Modeling",
ACM/IEEE International Workshop on System-Level Interconnect Prediction,
Sonoma, CA, (2001).
K. Rose, R. Mangaser, C. Mark, and E. Sayre, "Cryogenically Cooled CMOS", Critical Reviews in Solid State and Materials
Sciences, 24, (1), 63-99, (1999).
B. Geuskens and K. Rose, Modeling Microprocessor
Performance, Kluwer Academic Publishers, (1998).
K. Rose, T. Chiba, W.R. Heller, and W.F. Mikhail,
"Package Wiring and Terminals," in Microelectronics
Packaging Handbook, Second Edition, Part 1, R. R. Tummala, E.J.
Rymaszewski, A.G. Klopfenstein, eds, Chapman & Hall, (1997).
K. Rose, "Silicon-Based Semiconductors", in Kirk-Othmer Encyclopedia of Chemical Technology, Fourth Edition, J. Wiley & Sons, 720-750 (1997).(Recently revised with S. Devarajan, in press).
K. Rose, C.L. Bertin, and R.M. Katz, "Radiation
Detectors," in Applied Superconductivity, Academic Press,
6207 Low Center for Industrial Innovation
Rensselaer Polytechnic Institute
110 Eighth Street
Troy, N.Y. 12180 USA
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