Russell P. Kraft
Senior Project Manager, Adjunct Assistant Professor,
Rensselaer Polytechnic Institute
Ph.D., Electrical Engineering, Rensselaer Polytechnic Institute,
M. Eng., Electrical Engineering, Rensselaer Polytechnic Institute,
B.S., Electrical Engineering, Rensselaer Polytechnic Institute,
Kraft joined the research staff of the Center for Integrated Electronics
(CIE) in 1995. He currently also serves as an adjunct assistant
professor in the Electrical, Computer, and Systems Engineering Department
(ECSE) as well as the Computer Science Department.
He spent the previous nine years as senior project
manager for the Center for Manufacturing Productivity at Rensselaer.
Before joining the university, he served as a senior controls engineer
for the research and development division of Mechanical Technology
Inc., in Latham, N.Y. for four years. While a student at Rensselaer,
Kraft also taught courses in the ECSE department for two years.
Kraft has published over 40 conference articles
and 13 journal articles. He has seven other articles in preparation
and three in review in the Very Large Scale Integration (VLSI) area.
Kraft has two patents in the computer-vision area for non-contact
gauging and is co-author of several publications in machine vision,
ultrasonic imaging, phased array design, homomorphic signal processing
and control system design.
For the past several years, Kraft has been affiliated with the Defense
Advanced Research Projects Agency (DARPA) integrated circuit design
project for Fast Reduced Instruction Set Computer (RISC) design
using GaAs/AlGaAs Heterojunction Bipolar Transistor (HBT) technology.
This project is now fully involved in many aspects of the new IBM
SiGe HBT/CMOS technology through several generations of their commercially
available and unreleased design kits, which permit (VLSI) at tens
of gigahertz clock speeds. The high speed circuits being designed
have been expanded to include field programmable gate arrays (FPGAs),
field programmable analog arrays (FPAAs), analog to digital converters
(ADCs), serializer/deserializer (SERDES) communications circuits,
single event upset (SEU) tolerant logic, and clockless logic.
Kraft has extensive skills using COMPASS Tools,
CADENCE Integrated Circuit Design System, and MENTOR Computer Aided
Design Tools. His specialty is in evaluating the impact of interconnections
on architecture. He is certified to use Rensselaer's class 100 clean
room, where he has been involved in the design and process development
of a new 3D chip stacking process for higher integration and faster
Kraft has a broad background in research in robotics,
control systems analysis and design, ultrasonic imaging, phased
array design, digital and analog signal processing (linear signals
or images), as well as pattern recognition. Additionally, he has
practical experience in computer interfacing, integration, networking,
and real-time application programming on multiprocessor systems.
His background in control theory has been applied
to the design and fabrication of complete working systems while
managing teams of engineers, technicians, and students, both graduate
and undergraduate. He has also been involved with projects that
integrated servo controlled xyz and theta stages, analog data acquisition
boards, robots, and other special function peripherals with microprocessor
controllers and has directed as well as participated directly in
the development of the dedicated software used to drive all the
I. Fidan, E. Roush, S. Tumkor, and R.P. Kraft,
"Internet-Based Electronics Manufacturing Troubleshooting Tool for Surface Mount PCB Assembly",
International Journal of Advanced Manufacturing Technology, 2006, (27), 561-567, 2006.
P. Jacob, 0. Erdogan, A. Zia, P. M. Belemjian, R. P. Kraft, and J. F. McDonald, "
Predicting the Performance of a 3D Processor-Memory Chip Stack",
IEEE Design & Test of Computers, 22, (6), 540-547, November 2005.
P. Belemjian, O. Erdogan, R. P. Kraft, and J. F. McDonald,
"SiGe HBT Microprocessor Core Test Vehicle",
Proc. IEEE, 93, (9), 1669-1678, Sept. 2005.
C. You, J.-R. Guo, R. P. Kraft, M. Chu, P. Curran, K. Zhou, B. Goda and J.F. McDonald, "
A 5-10 GHz SiGe BiCMOS FPGA with New Configurable Logic Block", Microprocessors and Microsystems,
29, (2/3), 121-131, (April/May 2005)
M. Chu, R. Heikaus, R.-J. Guo, K. Zhou, C. You, J.F. McDonald and R.P. Kraft, "Ultra High Speed Interleaved A/D Conversion Using an fT Doubler Core in SiGe HBT Technology," Accepted by the IEEE Transactions on Instrumentation and Measurement.
J.-R. Guo, C. You, K. Zhou, M. Chu, P.F. Curran, J. Diao, B. Goda, R.P. Kraft and J.F. McDonald, "A 10GHz 4:1 MUX and 1:4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC," Integration, the VLSI Journal, 38,
(3), 525-540, (March, 2005).
K. Zhou, R.-J. Guo, C. You, J. Mayega, R.P. Kraft, T. Zhang, B.S. Goda, and J.F. McDonald, "
Multi-GHz SiGe BiCMOS FPGAs with New Architecture and Novel Power Management Techniques,"
World Scientific Journal of Circuits, Systems, and Computers, 14,
(2), 179-193, (2005).
T. W. Krawczyk, P.F. Curran, M.W. Ernest, S.A. Steidl, S.R. Carlough, J.F. McDonald, and R.P. Kraft,
"A Transmitter Architecture for High Speed, Short-Haul Serial Communication," IEE Proceedings Circuits, Devices & Systems,
151, (4), 315-321, (August 2004).
J. F. McDonald, R.P, Kraft, P. Belemjian, O. Erdogan, J.-Q. Lu, A.Y. Zheng, K. Rose, and R.J. Gutmann, "A Wafer Bonding Approach for 3D Processor Memory Chip-stacks," Proceedings of the 21st VLSI Multilayer Interconnect Conference (VMIC 04), Waikoloa Beach, HI, 225-230, (September 30-October 2, 2004).
J.-R. Guo, C. You, M. Chu, K. Zhou, J. Diao, B. Goda, R.P. Kraft, and J.F. McDonald, "A High Performance Field Programmable Gate Array For Gigahertz Applications," 2004 Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Washington, D.C., (Sept. 8-10, 2004)
Center for Integrated Electronics
Rensselaer Polytechnic Institute
110 Eighth Street
Troy, N.Y. 12180 USA
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