Christopher Carothers, Ph.D.

Professor, Rensselaer Polytechnic Institute

Large-Scale Static Timing Analysis in Support of Next Generation Computer Design

Top companies in Electronic Design and Automation (EDA), which focus on building software tools for the design of integrated circuits and microprocessors, represents a market capitalization that exceeds 20 billion dollars. Given the need to analyze circuits with billions of transistors, across potentially thousands of process corners at an accuracy tolerances down to the picosecond range, sequential execution of static timing analysis (STA) algorithms is quickly becoming a bottleneck to the overall chip design closure process. This research focuses on parallelization of the classic STA algorithm for verifying timing characteristics of digital integrated circuits. A message passing based parallel processing technique for performing STAleveraging an IBM Blue Gene/L supercomputing platform is presented.

Results are collected for two industrial 65 nm benchmarking designs. Using 1024 processors, the parallel timing algorithm achieves 173 times speedup on one benchmark and 217 times on the other. The prototype additionally employeed a parallel I/O approach to load two, billion node synthetic designs that are an order of magnitude larger than currently processed by EDA companies. With one of the billion node designs, the prototype demonstrates 12.3 times speedup as it scales from 1024 to 16,384 cores and 20.2 times speedup on the other billion node design as it scales from 512 to 16,384 cores.

With this improvement in both STA algorithm execution time and circuit size, there is the potential to shrink the overall time in the chip design process which leads to a faster time-to-market for chip design companies.


Dr. Carothers is a Professor in the Computer Science Department at Rensselaer Polytechnic Institute. He received the Ph.D., M.S., and B.S. from Georgia Institute of Technology in 1997, 1996, and 1991, respectively. Prior to joining RPI, he was a research scientist at the Georgia Institute of Technology. Dr. Carothers is an NSF CAREER Award winner as well as Best Paper award winner at the PADS workshop for 1999, 2003 and 2009. His research interests include massively parallel systems, high-performance modeling and simulation, networking, and computer architecture.

Workshop Program
updated: 2011-10-19