Ronald Gutmann and his colleagues in the Focus Center - New York at the Rensselaer Polytechnic Institute hope to make smaller, faster, and less expensive microelectronic circuits by creating them in three dimensions rather than the conventional flat-packed arrangement of today's circuits.

Processed Si wafer, supplied by SEMATECH, bonded to a glass wafer after the silicon was removed in the Focus Center-New York, Rensselaer Polytechnic Institute. Photo by Russ Kraft.

The researchers bond together several chip wafers and then use inter-wafer interconnects to make the links between layers. Such devices will dramatically improve performance and functionality, the researchers claim. The Rensselaer team led by Gutmann is collaborating with other universities and semiconductor industrial partners, such as the University at Albany, International SEMATECH, in Austin. "We're working with others to develop a very promising approach to building vertically integrated (3-D) circuits; going up, instead of across," explains Jian-Qiang 'James' Lu , who leads the processing team.

To make and interconnect 3-D chips, Lu explains, two chip wafers are aligned face-to-face and bonded together, and then the backside of the top wafer gets thinned. Finally, the inter-wafer interconnects are formed to connect these two wafers. Repeating this process flow, a third chip wafer (or more) can then be aligned, bonded, thinned, and interconnected vertically.

On conventional 2-D chips, there are already multilevel interconnects, which connect the single-layer active functional devices. But as more and faster devices get densely packed on chips, the time taken for a signal to travel from one device or device block on one side of the chip to that on another side becomes significant.

Gutmann and his colleagues reasoned that their approach to stacking smaller chips in 3-D would avoid this time lag by providing short inter-wafer interconnects between chip levels rather than a large chip with on-chip interconnects. This 3-D integration therefore offers significant performance increase for high-speed digital interconnects.

Mixing the systems on a 3-D chip will enable technology for future chips to be low-cost and will also allow nanoelectronic, opto-electronic, and biochemical circuits to be integrated into single systems, says Lu. With this 3-D technology off-the-shelf chips can be manipulated as individual layers and optimized and then interconnected.